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1. Field of the Invention
The invention relates generally to the field of electronic simulation tools and Electronic Design Automation (EDA). More particularly, the invention relates to co-/ multisimulation technology and automated design partitioning.
2. Description of the Related Art
A number of trends in the design verification market and technological factors are making it increasingly more desirable to be able to employ multiple simulation tools on the same design. For instance, simulation tools are becoming increasingly more specialized while the number of simulation products is steadily growing. Additionally, the simulation task is becoming more decentralized as designers of all types of electronic products are using simulation at every phase of the design process, from analyzing tradeoffs during early architectural analysis, through detailed design of digital and analog circuits to optimize performance and power dissipation, to verification of hardware and firmware for complete system emulation and test. Moreover, design complexity and design diversity are increasing and each design technology (e.g., IC design, board design, and system design) tends to have its own simulation tools, models and vendors. Therefore, a typical design process may incorporate multiple tools from multiple vendors.
Co-simulation, the verification of a design using two simulators concurrently in a simulation session is advantageous to designers in many ways. For example, by employing co-simulation techniques, a designer that is familiar with a particular simulator, such as Verilog-XL, may gain the benefits of additional simulation algorithms, such as Synopsys/EPIC""s TimeMill and/or IKOS""s NSIM, without leaving the Verilog environment. Additionally, in theory, designers gain the freedom to choose the best verification tools for each task during the design process.
However, co-simulation solutions thus far have several shortcomings. By way of example, simulator vendors typically offer xe2x80x9cgluedxe2x80x9d or xe2x80x9cmerged kernelxe2x80x9d products that are not based upon extensible technology. A typical prior glued approach involves the manual gluing together of two simulators through a Procedural Language Interface (PLI). Additionally, before co-simulation may begin, the designer must manually partition the design between the two simulators, e.g., by producing design source files usable by each simulator, and write special routines to facilitate the linkage and synchronization between the simulators. As a result, subsequent design modifications and/or partition changes to such a handstitched design results in numerous error prone manual steps to accomplish the necessary re-partitioning. Moreover, prior co-simulation solutions support only a simple all-or-nothing distribution of design objects (e.g., cell-based partitioning) among simulators and are therefore typically incapable of handling arbitrary partitions. Finally, prior co-simulation solutions do not preserve name space mapping across partitions. Consequently, during simulation, the user is required to perform manual signal name translations.
In light of the foregoing, what is needed is a simulation solution which provides an intelligent automated design partitioning mechanism.
A flexible and extensible automated design partitioning mechanism that facilitates simulation sessions employing two or more client simulators is described. According to one aspect of the present invention, the automated design partitioning mechanism is able to accomodate arbitrary (e.g., instance-based) partitioning. A design source expressed in a design representation upon which a first simulator may operate is received. Design blocks to be partitioned to each of a plurality of solvers are identified based upon one or more partitioning directives and the design source. A first instance of a cell is assigned to a first solver and a second instance of the cell is assigned to a second solver. Netlist like information is generated for those of the design blocks that are partitioned to a non-design source solver. To accomodate a folded representation of a design block containing the first or second instance of the cell, one or more additional cells are created.
According to another aspect of the present invention, name space mapping is retained across all simulators. A design source upon which a first simulator may operate is read. Based upon a set of rules, a primary partition that is to be simulated by a first solver is identified. The primary partition includes a top cell of the design representation. Additionally, a secondary partition that is to be simulated by a second solver is identified. Subsequently, netlist information is generated for the second solver while retaining name space mapping in the secondary partition by adding one or more levels of hierarchy so as to include information about the top cell in the secondary partition.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.